[1] Yagnesh Challagundla, Krishna Sai Devatha, Bharathi VC, JVR Ravindra, et al. “A Multi-Model Machine Learning Approach for Monitoring Calories Being Burnt During Workouts Using Smart Calorie Tracer.” In: EAI Endorsed Transactions on Pervasive Health & Technology 10.1 (2024).

 

[2] Hritwik Ghosh, Irfan Sadiq Rahat, MD Hasan Nipu, Garigipati Rama Krishna, JVR Ravindra, et al. “From Pixels to Pathology: The Power of CNNs in Detecting Tuberculosis.” In: EAI Endorsed Transactions on Pervasive Health & Technology 10.1 (2024).

 

[3] Hritwik Ghosh, Irfan Sadiq Rahat, Sachi Nandan Mohanty, JVR Ravindra, and Abdus Sobur. “A study on the application of machine learning and deep learning techniques for skin cancer detection”. In: International Journal of Computer and Systems Engineering 18.1 (2024), pp. 51– 59.

 

[4] Hritwik Ghosh, Irfan Sadiq Rahat, JVR Ravindra, Mohammad Aman Ullah Khan, J Somasekar, et al. “Convolutional Neural Networks in Malaria Diagnosis: A Study on Cell Image Classification.” In: EAI Endorsed Transactions on Pervasive Health & Technology 10.1 (2024).

 

[5] Irfan Sadiq Rahat, Tuhin Hossain, Hritwik Ghosh, Kamjula Lakshmi Kanth Reddy, Srinivas Kumar Palvadi, and JVR Ravindra. “Exploring Deep Learning Models for Accurate Alzheimer’s Disease Classification based on MRI Imaging.” In: EAI Endorsed Transactions on Pervasive Health & Technology 10.1 (2024).

 

[6] Saroja Kumar Rout, JVR Ravindra, Anudeep Meda, Sachi Nandan Mohanty, and Venkatesh Kavididevi. “A Dynamic Scalable Auto-Scaling Model as a Load Balancer in the Cloud Computing Environment.” In: EAI Endorsed Transactions on Scalable Information Systems 10.5 (2023).

 

[7] B Srikanth, JVR Ravindra, P Ramakrishna, and D Ajitha. “Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication”. In: Wireless Personal Communications (2023).

 

[8] B Srikanth, JVR Ravindra, P Ramakrishna, and D Ajitha. “Design and Implementation of PowerEfficient Cryptography Scheme Using a Novel Multiplication Technique”. In: Wireless Personal Communications 131.1 (2023), pp. 251–270.

 

[9] Subasish Mohapatra, Sarmistha Muduly, Subhadarshini Mohanty, JVR Ravindra, and Sachi Nandan Mohanty. “Evaluation of deep learning models for detecting breast cancer using histopathological mammograms Images”. In: Sustainable Operations and Computers 3 (2022), pp. 296– 302.

 

[10] Sangeeta Singh, JVR Ravindra, and B Rajendra Naik. “Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique”. In: International Journal of Integrated Engineering 14.1 (2022), pp. 374–388.

 

[11] Sangeeta Singh, JVR Ravindra, and B Rajendra Naik. “Design and implementation of network-onchip router using multi-priority based iterative round-robin matching with slip”. In: Transactions on Emerging Telecommunications Technologies (2022), e4514.

 

[12] Sangeeta Singh, JVR Ravindra, and B Rajendra Naik. “Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip”. In: International Journal of Computer Network and Information Security 14.4 (2022), p. 75.

 

[13] Sangeetha Singh, JVR Ravindra, and B. Rajendra Naik. “Proffering secure energy aware Networkon-Chip (Noc) using incremental Cryptogine”. In: Sustainable Computing: Informatics and Systems 2.9 (2022).

 

[14] Lavanya Maddisetti, Ranjan K Senapati, and JVR Ravindra. “Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor”. In: Computers & Electrical Engineering 92 (2021), p. 107137.

 

[15] Lavanya Maddisetti, Ranjan K Senapati, and JVR Ravindra. “Improvement in the accuracy of Binary Neural Network based 4:2 Compressor using De-noising technique”. In: Journal of Biological Engineering Research and Review 8.2 (2021), pp. 61–65.

 

[16] C Padmini and JVR Ravindra. “Secured Substitution Box of Advance Encryption Standards (AES) With Permutation”. In: International Journal of Research in Engineering and Science (IJRES) 9.6 (2021).

 

[17] C Padmini and JVR Ravindra. “Leakage Resilient Adder using Dual Rail, Single Clock Adiabatic Logic against DPA Attacks”. In: Elsevier, International Journal of Advanced Science and Technology 29.4 (2020), pp. 6120–6133.

 

[18] G Rajesh and JVR Ravindra. “Design of High Speed and Low Power Differential Voltage Charge Sharing Comparator using Small Swing Domino Logic”. In: International Journal of Advanced Trends in Computer Science and Engineering 9.3 (2020).

 

[19] B Srikanth, M Siva Kumar, JVR Ravindra, and K Hari Kishore. “The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model”. In: Transactions on Emerging Telecommunications Technologies (2020), e3948.

 

[20] R Phani Vidyadhar, P Ganga Kiran, E Pranavi, J Ashwitha, and JVR Ravindra. “Noninvasive design of low-cost foot therapy BOT for plantar fasciitis”. In: Int J 9 (2020), pp. 4153–4157.

 

[21] Akshitha Vuppala, R Sai Roshan, Shaik Nawaz, and JVR Ravindra. “An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm”. In: Elsevier, Procedia Computer Science 171 (2020), pp. 1054–1063.

 

[22] JVR Ravindra M. Lavanya RK Senapati. “Training neural network as approximate 4:2 compressor applying machine learning algorithms for accuracy comparison”. In: International Journal of Advanced Trends in Computer Science and Engineering 8.2 (2019), pp. 211–215.

 

[23] L. Maddisetti, R.K. Senapati, and JVR Ravindra. “Supervised machine learning for training a neural network as 5:2 compressor”. In: International Journal of Innovative Technology and Exploring Engineering 8.10 (2019), pp. 2079–2084.

 

[24] Sangeetha Singh, JVR Ravindra, and B. Rajendra Naik. “Power and area optimized FRA-CSLA for high-speed NoC applications”. In: International Journal of Advanced Trends in Computer Science and Engineering 8.3 (2019), pp. 883–888.

 

[25] Srikanth and K L University, Guntur, Andhra Pradesh, India. “Double Precession Floating Point Multiplier using Schonhage – Strassen Algorithm used for FPGA Accelerator”. In: Int. J. Emerg. Trends Eng. Res. 7.11 (Nov. 2019), pp. 677–684.

 

[26] T Thanmai, Ch Nandini, N Pooja, and JVR Ravindra. “LI-PAMB: Low Complexity Implementation of Power and Area-efficient Modified Baugh Wooley Multiplier using Exact Computing”. In: International Journal of Simulation Systems, Science & Technology 20.6 (2019), pp. 9–1.

 

[27] M Lavanya, Ranjan K Senapati, and JVR Ravindra. “Low-power near-explicit 5: 2 compressor for superior performance multipliers”. In: International Journal of Engineering 11.4 (2018), pp. 529– 545.

 

[28] B Srikanth, M Siva Kumar, K Hari Kishore, and JVR Ravindra. “Towards reducing area and power of a multiplier with double precision floating point computations using FPGA accelerators”. In: Journal of Advanced Research in Dynamical and Control Systems 9.18 (2017), p. 2780.

 

[29] M Anil Kumar and J Ravindra. “4×4 MIMO Alamouti Decoder Implementation Using VERTEX2”. In: International Journal & Magazine of Engineering, Technology, Management and Research 3.12 (2016), pp. 67–73.

 

[30] Ch Ashok Babu, JVR Ravindra, and K Lalkishore. “Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits”. In: Circuits and Systems 6.03 (2015), p. 60.

 

[31] A Aruna Sree and JVR Ravindra. “Realization Of Fir Filter By An Efficient And Flexible Systemization Using Distributed Arithmetic”. In: (2015).

 

[32] Ch Ashok Babu, JVR Ravindra, and K Lal Kishore. “An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology”. In: Global Journals of Research in Engineering 13.F14 (2013), pp. 27–30.

 

[33] Ch Ashok Babu, JVR Ravindra, and Kishore K Lal. “An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology”. In: The Global Journal of Research in Engineering (GJRE) 2.4 (2013), pp. 23–41.

 

[34] CH Ashok Babu, JVR Ravindra, and K Lal Kishore. “Novel Circuit Level Leakage Power Reduction Technique for Ultra Low Power and high speed VLSI circuits”. In: International Journal of Communication Engineering Applications 3 (2012), pp. 508–514.

 

[35] Ehsan Rasekh and Anestis Dounavis. “A multidimensional krylov reduction technique with constraint variables to model nonlinear distributed networks”. In: IEEE transactions on advanced packaging 33.3 (2010), pp. 738–746.

 

[36] Sandeep Saini. “A Novel Approach to reduce Delay and Power in VLSI Interconnects”. In: Diss. International Institute of Information Technology Hyderabad, INDIA (2010).

 

[37] JVR Ravindra and MB Srinivas. “Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency Shift Technique”. In: International Journal of Electronics, Circuits and Systems 2 (2008), p. 4.

 

[38] JVR Ravindra, Sandeep Saini, Avinash Shukla, and MB Srinivas. “Sign Extension Based Method Low Power Fast Fourier Transform”. In: ISOCC (2007), pp. 135–138.

 

[39] JVR Ravindra and MB Srinivas. “Delay and energy efficient coding techniques for capacitive interconnects”. In: Journal of Circuits, Systems, and Computers 16.06 (2007), pp. 929–942.

 

[40] KS Sainarayanan, C Raghunandan, JVR Ravindra, and MB Srinivas. “Modified Area Efficient Temporal Coding Technique for Delay Minimization in VLSI interconnects”. In: ISOCC (2006), pp. 173–176.

 

[41] KS Sainarayanan, JVR Ravindra, and MB Srinivas. “A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Interconnects”. In: (2006).

 

[42] JVR Ravindra, KS Sainarayanan, and MB Srinivas. “EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications”. In: ISOCC (2005), pp. 373–376.

 

[43] KS Sainarayanan, JVR Ravindra, and MB Srinivas. “A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI”. In: Interconnects Center for VLSI and Embedded System Technologies (CVEST) (2005).