[1] Cheruku Navaneeth Kumar Goud, Ch Kavya, S Bharath, and JVR Ravindra. “Optimized LowPower FIR Filter Design Using Residue Number System for Energy-Efficient DSP Applications”. In: 2025 International Conference on Inventive Computation Technologies (ICICT). IEEE. 2025, pp. 1681–1686.

 

[2] Bibhuprasad Sahu, Swagatika Dalai, Amrutanshu Panigrahi, Abhilash Pati, Chetan Aher, and JVR Ravindra. “Binary Learning Cooking Algorithm with Relief for Feature Selection of Highdimensional Gene Expression Data”. In: 2025 International Conference on Emerging Smart Computing and Informatics (ESCI). IEEE. 2025, pp. 1–6.

 

[3] Bibhuprasad Sahu, Sanjay Kumar Sen, Amrutanshu Panigrahi, Abhilash Pati, Ghanashyam Sahoo, and JVR Ravindra. “Ensemble Transfer Learning Coupled Osprey Optimization Algorithm for Feature Selection from Skin Cancer Image Datasets”. In: 2025 Fourth International Conference on Smart Technologies, Communication and Robotics (STCR). IEEE. 2025, pp. 1–6.

 

[4] Sanam Abhishek, Krishna Chaithanya Janapati, JVR Ravindra, Satyarth Motupalli, Bondugula Karthik Reddy, Godugu Suresh, and Vatsal A Dharek. “Design and Implementation of WiFiControl Robotic Arm for Cleaning Blackboard”. In: International Conference on Broadband Communications, Networks and Systems. Springer Nature Switzerland Cham. 2024, pp. 3–14.

 

[5] RV Prasad Bhookya and JVR Ravindra. “Design of high speed hybrid full adder using reversible logic gates”. In: AIP Conference Proceedings. Vol. 2942. 1. AIP Publishing LLC. 2024, p. 020017.

 

[6] Yagnesh Challagundla, Shreeya Dheera Parvatham, Sachi Nandan Mohanty, and JVR Ravindra. “Deep Learning-Driven Surveillance for Intrusion Identification using Proactive Intelligent Video Recognition”. In: 2024 IEEE International Conference on Advanced Video and Signal Based Surveillance (AVSS). IEEE. 2024, pp. 1–5.

 

[7] Krishna Chaitanya Janapati, JVR Ravindra, Satyarth Motupalli, Veda Manogna Nanduri, Pavani Punem, Sameer Mohammad, Sujay Kapil Peddaraju, and Amit Lathigara. “Supervene Bag A Smart Luggage Carrier”. In: International Conference on Broadband Communications, Networks and Systems. Springer Nature Switzerland Cham. 2024, pp. 260–271.

 

[8] G Kavya, K Shreshta Reddy, D Vishnu Prasad, JVR Ravindra, and Himanshu Rajeshbhai Dodiya. “Design and Implementation of Unsigned Serial Divider Using TG Logic”. In: International Conference on Broadband Communications, Networks and Systems. Springer Nature Switzerland Cham. 2024, pp. 42–50.

 

[9] G Kavya, K Shreshta Reddy, D Vishnu Prasad, and JVR Ravindra. “Enhancing Computational Speed Through Quantum Computing Techniques in Multiplier Design”. In: EAI International Conference on Intelligent Systems with Applications in Communications, Computing and IoT. Springer Nature Switzerland Cham. 2024, pp. 219–232.

 

[10] T Murali Krishna, Issam Trrad, Cholleti Harish, Hamsa Nimer, Hashem Al-Mattarneh, JVR Ravindra, et al. “Efficient Energy Management Algorithm for Single Stage SPV Based Water Pumping System Without Batteries”. In: 2024 International Conference on Sustainable Power & Energy (ICSPE). IEEE. 2024, pp. 1–6.

 

[11] Satyarth Motupalli, JVR Ravindra, GAE Satish Kumar, R Phani Vidhyadhar, Ramavathar Yadav Kanneboina, Varun Kumar Reddy, and Siddarth Tammineni. “Smart Drowsiness Detection System with Microcontroller Integration”. In: International Conference on Broadband Communications, Networks and Systems. Springer Nature Switzerland Cham. 2024, pp. 241–248.

 

[12] Dibyalekha Nayak, Tejaswini Kar, Kananbala Ray, JVR Ravindra, and Sachi Nandan Mohanty. “Hybrid Image Compression Using DCT and Autoencoder”. In: 2024 IEEE Pune Section International Conference (PuneCon). IEEE. 2024, pp. 1–6.

 

 

[13] JVR Ravindra, GAE Satish Kumar, and MA Jabbar. “Preface: 2nd International Conference on Advances in Signal Processing, VLSI, Communication and Embedded Systems”. In: AIP Conference Proceedings. Vol. 2942. 1. AIP Publishing LLC. 2024, p. 010001.

 

[14] Bibhuprasad Sahu, Sasmita Pani, Amrutanshu Panigrahi, Abhilash Pati, Rashmi Rani Patro, and JVR Ravindra. “A hybrid particle swarm optimization with binary Ali Baba and the forty thieves algorithm for feature selection”. In: 2024 3rd Odisha International Conference on Electrical Power Engineering, Communication and Computing Technology (ODICON). IEEE. 2024, pp. 1–6.

 

[15] Hitesh Kumar Sharma, Tanupriya Choudhury, JVR Ravindra, and Sachi Nandan Mohanty. “Geolocation based convalescent plasma locator system for treatment of COVID-19 disease”. In: AIP Conference Proceedings. Vol. 2942. 1. AIP Publishing LLC. 2024, p. 020027.

 

[16] B Srikanth, JVR Ravindra, GAE Satish Kumar, and Fahimuddin Shaik. “Implementation of Improved High Speed SHA-256 Algorithm from RTL to GDSII Using Verilog HDL”. In: Modern Approaches in Machine Learning and Cognitive Science: A Walkthrough: Volume 4. Springer International Publishing Cham, 2024, pp. 1–17.

 

[17] R Phani Vidyadhar, JVR Ravindra, GAE Satish Kumar, Yanigandla Sandeep, Kanugula Ashwitha, Devansh Mantri, and Faldu Vishvakumari. “Innovative Motion Sensing System with Labview”. In: International Conference on Broadband Communications, Networks and Systems. Springer Nature Switzerland Cham. 2024, pp. 249–259.

 

[18] Rishitha Kommineni, Gurram Arunsai, and JVR Ravindra. “Low Power, Noise-Immune High Performance Arithmetic Adder Circuit Design Using Modified Parallel Prefix Adders”. In: Inventive Communication and Computational Technologies: Proceedings of ICICCT 2022. Springer Nature Singapore, 2023, pp. 763–775.

 

[19] Bibhuprasad Sahu, Chakradharamahanthi Madhavi, Sasmita Pani, and JVR Ravindra. “Binary Optimization Using Hybrid Owl Optimization For Biomarker Selection From Cancer Datasets”. In:2023 IEEE 3rd International Conference on Technology, Engineering, Management for Societal impact using Marketing, Entrepreneurship and Talent (TEMSMET). IEEE. 2023, pp. 1–6.

 

[20] Bibhuprasad Sahu, JVR Ravindra, Sachi Nandan Mohanty, and Amrutanshu Panigrahi. “Hybrid grasshopper optimization algorithm with simulated annealing for feature selection using high dimensional dataset”. In: 2023 1st International Conference on Advanced Innovations in Smart Cities (ICAISC). IEEE. 2023, pp. 1–6.

 

[21] Bibhuprasad Sahu, Saroja Kumar Rout, JVR Ravindra, and Sachi Nandan Mohanty. “Multi-filter enhanced doctor and patient optimization algorithm for cancer diagnosis”. In: Proceedings of the International Health Informatics Conference: IHIC 2022. Springer Nature Singapore Singapore. 2023, pp. 69–78.

 

[22] Gunda Sowmya, Sulguti Sai Sowmya, and JVR Ravindra. “Efficient RNS Realization of High-Speed Arithmetic Multiplier with Respect to Cryptographic Computation”. In: Inventive Communication and Computational Technologies: Proceedings of ICICCT 2022. Springer Nature Singapore, 2023, pp. 13–21.

 

[23] S Sujana, Durga Bhavani Kinthadi, and JVR Ravindra. “Feature Level Fusion of Face and Fingerprint Biometric Traits for Universality”. In: 2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS). IEEE. 2023, pp. 199–204.

 

[24] Mahankali Mani Teja, JVR Ravindra, Sunku Rohan Sanjay Reddy, and Irugurala Yashwanth. “Quantum Modular Multiplication: A New Frontier in Quantum Computing”. In: 2023 IEEE 8th International Conference for Convergence in Technology (I2CT). IEEE. 2023, pp. 1–7.

 

[25] Sirisha Potluri, JVR Ravindra, Gouse Baig Mohammad, and Guna Sekhar Sajja. “Optimized Test Coverage With Hybrid Particle Swarm Bee Colony And Firefly Cuckoo Search Algorithms In Model Based Software Testing”. In: 2022 First International Conference on Artificial Intelligence Trends and Pattern Recognition (ICAITPR). Vol. 1. 1. 2022, pp. 1–9.

 

[26] Bibhuprasad Sahu, Swarupa Pattanaik, JVR Ravindra, and Sasmita Pani. “Detection of Disease Through Clinical Data Using Light Intensity Based Firefly Algorithm”. In: 2022 International Conference on Futuristic Technologies (INCOFT). IEEE. 2022, pp. 1–8.

 

[27] P Srinivasa Rao, S Venukumar, Mukul Shrivastava, K Deepak, Begori Venkatesh, and P Venkateshwar Reddy. “Preface: 4th International Congress on Advances in Mechanical Sciences (ICAMS 2021)”. In: AIP Conference Proceedings. Vol. 2648. 1. AIP Publishing LLC. 2022, p. 010002.

 

[28] Thogiti Sai Aditya Teja, G Sai Teja, JVR Ravindra, and Lavanya Maddisetti. “High Speed Multiplier using Embedded Approximate 4-2 Compressor for Image Multiplication”. In: 2022 First International Conference on Artificial Intelligence Trends and Pattern Recognition (ICAITPR). Vol. 1. 1. 2022, pp. 1–5.

 

[29] Swathi Vangala, Rishi Kiran E, and JVR Ravindra. “QUEST: Quantum Computing-Based Reversible Hybrid Encoder/Decoder for Error Resilient Transmission”. In: Soft Computing and Signal Processing. Springer, Singapore, 2022, pp. 497–505.

 

[30] Lanka Sai Charan, M Vaishnavi Reddy, N Pooja Reddy, and JVR Ravindra. “5: 3 compressor based neural network with LM Algorithm in Multiplier as Application”. In: IOP Conference Series: Materials Science and Engineering. Vol. 1042. 1. IOP Publishing. 2021, p. 012033.

 

[31] S Deepak, Ganesan SaiKrishnan, D Rajesh, and JVR Ravindra. “Seek-method based 2’s complement circuit for low power circuit and high-speed operation”. In: AIP Conference Proceedings. Vol. 2407. 1. AIP Publishing LLC. 2021, p. 020008.

 

[32] G Harika, V Ananya, V Harshitha, and JVR Ravindra. “Router design for rhombic topology in Network-on-Chip”. In: AIP Conference Proceedings. Vol. 2407. 1. AIP Publishing LLC. 2021, p. 020029.

 

[33] E Rishi Kiran, Swathi Vangala, and JVR Ravindra. “PERAM: Ultra Power Efficient Array Multiplier Using Reversible Logic for High-Performance MAC”. In: Inventive Communication and Computational Technologies. Vol. 145. Springer, Singapore, 2021, pp. 747–756.

 

[34] Lavanya Maddisetti, Ranjan K Senapati, and JVR Ravindra. “A Neural Network trained to perform as an Imprecise 4: 2 Compressor using Machine Learning Algorithm”. In: IOP Conference Series: Materials Science and Engineering. Vol. 1042. 1. IOP Publishing. 2021, p. 012014.

 

[35] Lavanya Maddisetti, Ranjan K Senapati, and JVR Ravindra. “Image multiplication with a powerefficient approximate multiplier using a 4: 2 compressor”. In: Advances in Image and Data Processing using VLSI Design, Volume 1: Smart vision systems. IOP Publishing Bristol, UK, 2021, pp. 13–1.

 

[36] C Padmini and JVR Ravindra. “Design of leakage resilient and DPA attack immune architecture of S BOX”. In: 2021 6th International Conference on Communication and Electronics Systems (ICCES). IEEE. 2021, pp. 936–944.

 

[37] P Sai Prasanna, B Rithvej, and JVR Ravindra. “Conversion of mealy to Moore machine for safety critical systems”. In: AIP Conference Proceedings. Vol. 2407. 1. AIP Publishing LLC. 2021, p. 020015.

 

[38] JVR Ravindra. “Preface: 1st International Conference on Advances in Signal Processing, VLSI, Communications and Embedded Systems (ICSVCE-2021)”. In: American Institute of Physics Conference Series. Vol. 2407. 1. 2021, p. 010001.

 

[39] M Vaishnavi Reddy, N Sai Pooja Reddy, and JVR Ravindra. “UBAPS: Inexact Unsigned Binary 5: 2 Compressor Towards Power Efficient and High Speed for Three-Stage FIR Filter”. In: Inventive Communication and Computational Technologies. Vol. 145. Springer, Singapore, 2021, pp. 607– 617.

 

[40] S Thanusha Reddy, K Lakshmimanasa, M Divya Sree, and JVR Ravindra. “A novel designing of low power Schmitt Trigger using DFAL technique”. In: AIP Conference Proceedings. Vol. 2407.1. AIP Publishing LLC. 2021, p. 020024.

 

[41] R Sai Roshan, S Nawaz, A Vuppala, and JVR Ravindra. “Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs”. In: 3rd International Conference on Computing and Communication Systems (I3CS). Lecture Notes in Networks and Systems, 2021, pp. 661–668.

 

[42] G Santhosh Reddy, K Sai Vandana, SVR Subramanya Sai, and JVR Ravindra. “Efficient Design of MISTO CDL Adder Cell for High Throughput and Power-Efficient Array Divider”. In: Soft Computing and Signal Processing: Proceedings of 3rd ICSCSP 2020, Volume 1. Springer Singapore Singapore, 2021, pp. 595–605.

 

[43] T Thanmai and JVR Ravindra. “High performance, low power architecture of 5-stage fir filter using modified montgomery multiplier”. In: 2020 International Conference on Applied Electronics (AE). IEEE. 2020, pp. 1–5.

 

[44] Lavanya Maddisetti and JVR Ravindra. “Low-power. high-speed adversarial attack based 4: 2 compressor as full adder for multipliers in fir digital filters”. In: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. 2019, pp. 1–6.

 

[45] Lavanya Maddisetti and JVR Ravindra. “Machine learning based power efficient approximate 4: 2 compressors for imprecise multipliers”. In: 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID). IEEE Computer Society. 2019, pp. 221–226.

 

[46] M Lavanya and JVR Ravindra. “Performance metrics of imprecise multipliers based on proximate compressors for IIR filters”. In: 2018 30th International Conference on Microelectronics (ICM). IEEE. 2018, pp. 96–99.

 

[47] Lavanya Maddisetti and JVR Ravindra. “Performance metrics of inexact multipliers based on approximate 5: 2 compressors”. In: 2018 International SoC Design Conference (ISOCC). IEEE. 2018, pp. 84–85.

 

[48] S Sai Satyanarayana Reddy, JVR Ravindra, N Hanuman Reddy, and Anji Reddy Polu. “A novel nanocomposite polymer electrolyte for application in solid state lithium ion battery”. In: 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO). IEEE. 2018, pp. 1–4.

 

[49] Srimai Inapurapu and JVR Ravindra. “NEON: Near-accurate efficient FIR Filter for ultra lowpower applications”. In: 2016 International Conference on Applied Electronics (AE). IEEE. 2016, pp. 97–101.

 

[50] C Padmini and JVR Ravindra. “CALPAN: Countermeasure against leakage power analysis attack by normalized DDPL”. In: 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE. 2016, pp. 1–7.

 

[51] C Padmini and JVR Ravindra. “PEARL: Performance analysis of ultra low power reversible logic circuits against DPA attacks”. In: 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE. 2016, pp. 4344–4349.

 

[52] Chiranjeevi Sheelam and JVR Ravindra. “A novel and efficient design of golay encoder for ultra deep submicron technologies”. In: 2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE. 2016, pp. 275–280.

 

 

[53] Sangeeta Singh, JVR Ravindra, and B Rajendra Naik. “Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip”. In: 2016 International SoC Design Conference (ISOCC). IEEE. 2016, pp. 5–6.

 

[54] Srimai Inapurapu, JVR Ravindra, and S Sai Satyanarayana Reddy. “JARVIS: Just-Accurate Competent IIR Filter Using Proximate Reversible Adder for Low-Power Applications”. In: 2015 Seventh International Conference on Computational Intelligence, Modelling and Simulation (CIMSim). IEEE. 2015, pp. 149–154.

 

[55] Abdul Mosin and JVR Ravindra. “A novel polynomial basis multiplier for arbitrary elliptic curves over GF (2 m)”. In: International Conference for Convergence for Technology-2014. IEEE. 2014, pp. 1–3.

 

[56] Gangadhar Reddy Ramireddy and JVR Ravindra. “A novel power-aware and high performance full adder cell for ultra-low power designs”. In: 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014]. IEEE. 2014, pp. 1121–1126.

 

[57] N Sainath Reddy and JVR Ravindra. “A novel modulo 2 n+ 1 fused multiply-adder unit for secured VLSI architectures”. In: 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014]. IEEE. 2014, pp. 1302–1306.

 

[58] Narasimha Rao Konijeti, JVR Ravindra, and Pandurangaiah Yagateela. “Power aware and delay efficient hybrid CMOS full-adder for ultra deep submicron technology”. In: 2013 European Modelling Symposium. IEEE. 2013, pp. 697–700.

 

[59] Gangadhar Reddy Ramireddy, JVR Ravindra, and Harikrishna Kamatham. “Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style”. In: 2013 European Modelling Symposium. IEEE. 2013, pp. 691–696.

 

[60] JVR Ravindra and Gangadhar Reddy Ramireddy. “HarikrishnaKamatham,“”. In: Design of Ultra Low Power Full Adder using Modified Branch Based Logic Style,” IEEE European Modelling Symposium. 2013, pp. 691–696.

 

[61] JVR Ravindra, Pandurangaiah Yagateela, and Narasimha Prasad. “A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications”. In: 2013 UKSim 15th International Conference on Computer Modelling and Simulation. IEEE. 2013, pp. 798–802.

 

[62] JVR Ravindra and MB Srinivas. “11th IEEE Workshop on Signal Propagation on Interconnects”. In: 2011.

 

[63] JVR Ravindra and MB Srinivas. “Performance modeling of high speed VLSI interconnects”. In: 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia). IEEE. 2010, pp. 61–64.

 

[64] JVR Ravindra and Mandalika Srinivas. “Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits”. In: Proceedings of the 18th ACM Great Lakes symposium on VLSI. 2008, pp. 111–114.

 

[65] JVR Ravindra and MB Srinivas. “Generating reduced order models for high speed VLSI interconnects using balancing-free square root method”. In: 2008 12th IEEE Workshop on Signal Propagation on Interconnects. IEEE. 2008, pp. 1–4.

 

[66] JVR Ravindra and MB Srinivas. “Static Superelement Technique based Macromodeling for High Speed Nano Designs”. In: 2008 8th IEEE Conference on Nanotechnology. IEEE. 2008, pp. 745–747.

 

[67] JVR Ravindra and Srinivas Bala Mandalika. “Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach”. In: Proceedings of the 20th annual conference on Integrated circuits and systems design (SBCCI’07). ACM. 2007, pp. 207–211.

 

[68] JVR Ravindra and MB Srinivas. “A statistical model for estimating the effect of process variations on delay and slew metrics for VLSI interconnects”. In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE. 2007, pp. 325–330.

 

[69] JVR Ravindra and MB Srinivas. “Analytical crosstalk model with inductive coupling in VLSI interconnects”. In: 2007 IEEE Workshop on Signal Propagation on Interconnects. IEEE. 2007, pp. 221–224.

 

[70] JVR Ravindra and MB Srinivas. “Delay and slew analysis of VLSI interconnects using difference model approach”. In: 2007 50th Midwest Symposium on Circuits and Systems. IEEE. 2007, pp. 1313–1315.

 

[71] JVR Ravindra and MB Srinivas. “Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs”. In: Proceedings of the 2nd international conference on Nano-Networks. 2007, pp. 1–5.

 

[72] JVR Ravindra and MB Srinivas. “Model Order Reduction for RLC Interconnects using Response Dependent Condensation”. In: TENCON 2007-2007 IEEE Region 10 Conference. IEEE. 2007, pp. 1–4.

 

[73] JVR Ravindra and MB Srinivas. “Modeling of Full-Wave High Speed On-Chip RLC Interconnects using Frequency Shift Technique”. In: 2007 9th Electronics Packaging Technology Conference. IEEE. 2007, pp. 257–261.

 

[74] JVR Ravindra and MB Srinivas. “Response Dependent Condensation based macromodeling for linear time varying high speed VLSI interconnects”. In: 2007 International Symposium on Communications and Information Technologies. IEEE. 2007, pp. 44–48.

 

[75] KS Sainarayanan, C Raghunandan, JVR Ravindra, and MB Srinivas. “Bus coding to minimize redundant bit transitions”. In: TENCON 2007-2007 IEEE Region 10 Conference. IEEE. 2007, pp. 1–6.

 

[76] KS Sainarayanan, C Raghunandan, JVR Ravindra, and MB Srinivas. “Bus Coding to Minimize Redundant Bit Transitions, proc”. In: TENCON, IEEE Region-10. Vol. 10. 2007, pp. 1–6.

 

[77] KS Sainarayanan, JVR Ravindra, C Raghunandan, and MB Srinivas. “Coupling aware energyefficient data scrambling on memory-processor interfaces”. In: 2007 International Conference on Industrial and Information Systems. IEEE. 2007, pp. 421–426.

 

[78] Kiran T. Nath, KS Sainarayanan, JVR Ravindra, and MB Srinivas. “Coding for Minimizing Energy in VLSI Interconnects”. In: In 18th IEEE International Conference on Microelectronics (ICM). Vol. 18. IEEE. 2006, pp. 16–19.

 

[79] JVR Ravindra, Navya Chittarvu, and MB Srinivas. “Energy efficient spatial coding technique for low power VLSI applications”. In: 2006 6th International Workshop on System on Chip for Real Time Applications. IEEE. 2006, pp. 201–204.

 

[80] KS Sainarayanan, C Raghunandan, JVR Ravindra, and MB Srinivas. “Efficient Spatial-Temporal Coding Scheme for Minimizing Delay in Interconnects”. In: TENCON 2006-2006 IEEE Region 10 Conference. IEEE. 2006, pp. 1–4.

 

[81] KS Sainarayanan, JVR Ravindra, Kiran T Nath, and MB Srinivas. “Coding for minimizing energy in VLSI interconnects”. In: 2006 International Conference on Microelectronics. IEEE. 2006, pp. 166–169.

 

[82] KS Sainarayanan, JVR Ravindra, Kiran T Nath, and MB Srinivas. “Crosstalk Aware Low Power Bus Coding for VLSI Interconnects”. In: 2006 International Conference on Microelectronics. 2006.

 

[83] KS Sainarayanan, JVR Ravindra, and MB Srinivas. “A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects”. In: 2006 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. 2006, 4–pp.

 

[84] KS Sainarayanan, JVR Ravindra, and MB Srinivas. “Minimizing simultaneous switching noise (SSN) using modified odd/even bus invert method”. In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA’06). IEEE. 2006, 4–pp.

 

[85] JVR Ravindra, KS Sainarayanan, and MB Srinivas. “A novel bus coding technique for low power data transmission”. In: IEEE symposium on VLSI design and test conference (VDAT-2005). 2005, pp. 263–266.

 

[86] JVR Ravindra, KS Sainarayanan, and MB Srinivas. “An efficient power reduction technique for low power data I/O for military applications”. In: 24th Digital Avionics Systems Conference. Vol. 2. IEEE. 2005, 8–pp.

 

[87] KS Sainarayanan, JVR Ravindra, and MB Srinivas. “A novel deep submicron low power bus coding technique.” In: Circuits, Signals, and Systems. 2005, pp. 154–159.